I need help putting this serial adder block diagram into multisim software I ELE230L Digital Systems Design Laboratory Lab9 - Serial Adder Vaughn College of Aeronautics and Technology Number of Lab Session (Week): 2 1 Discussion The purpose of this lab is to design, simulate, and implement a 4-bit serial adder SADD. A block diagram is shown below. The SADD has two int bit FA with a carry-hold flip-flop. Its input is a 4-bit data input (D-Do), a rising edge sensitive clock signal (CLK), two clock enable signals (CEA and CEB), a parallel load/shift selector (LOADH _SHIFTL) an asynchronous reset signal (CLR). It outputs bit-by-bit to the 4-bit shift register A (QAy-QAo) and 4 bit shift register B (QB3-QBo). Both of them are used to store the result of the addition. ernal 4-bit shift registers (REGA and REGB), a single 1 Do CLK CEA CE SREGA LOAD CLR QA-QAg LOAD CLR QB-QB CEB LOADH SHIFTL CLR A B ICE FDCE FA CLR SUM Figure 1: Block Diagram of Serial Adder The clock-enable signals are passed to the internal registers. They are used to enable/disable data coming into the corresponding register (high - enable), i.e. if the clock-enable signal in the corresponding shift register is low (disabled), the register does not change state even though the clock signal changes. This allows us to work on one register while the other remains unchanged. Operation begins with resetting the adder by setting the CLR line high then dropping it low again. The reset signal clears the registers and the carry-hold flip-flops. I ELE230L Digital Systems Design Laboratory Lab9 - Serial Adder Vaughn College of Aeronautics and Technology Number of Lab Session (Week): 2 1 Discussion The purpose of this lab is to design, simulate, and implement a 4-bit serial adder SADD. A block diagram is shown below. The SADD has two int bit FA with a carry-hold flip-flop. Its input is a 4-bit data input (D-Do), a rising edge sensitive clock signal (CLK), two clock enable signals (CEA and CEB), a parallel load/shift selector (LOADH _SHIFTL) an asynchronous reset signal (CLR). It outputs bit-by-bit to the 4-bit shift register A (QAy-QAo) and 4 bit shift register B (QB3-QBo). Both of them are used to store the result of the addition. ernal 4-bit shift registers (REGA and REGB), a single 1 Do CLK CEA CE SREGA LOAD CLR QA-QAg LOAD CLR QB-QB CEB LOADH SHIFTL CLR A B ICE FDCE FA CLR SUM Figure 1: Block Diagram of Serial Adder The clock-enable signals are passed to the internal registers. They are used to enable/disable data coming into the corresponding register (high - enable), i.e. if the clock-enable signal in the corresponding shift register is low (disabled), the register does not change state even though the clock signal changes. This allows us to work on one register while the other remains unchanged. Operation begins with resetting the adder by setting the CLR line high then dropping it low again. The reset signal clears the registers and the carry-hold flip-flops.